Memory in a computer system may be arranged in a memory hierarchy including memory devices of different speeds and sizes. The type and size of a memory device and its proximity to the processor core are factors in the speed of the memory device. Generally smaller hardware is faster, and memory devices closest to the processor core are accessed fastest. Since fast memory may be expensive and space near the processor core limited, a memory hierarchy may be organized into several levels, each smaller, faster, and more expensive per byte than the next level. The goal of such a memory hierarchy is to provide a memory system with a cost almost as low as the cheapest level of memory and speed almost as fast as the fastest level of memory.
Many processors use memory caches to store copies of the most used data and instructions in order to improve access speed and overall processing speed. A memory cache, also referred to as cache store or RAM (Random Access Memory) cache, is a portion of memory which may be made of high-speed static RAM (SRAM) instead of the slower dynamic RAM (DRAM) used for main memory. Memory caches may be included at the highest level of memory and on the same integrated circuit (IC) as the processor. Such internal memory caches are also referred to as local or Level 1 (L1) caches.
The contents of the L1 cache may change depending on the task being performed by the processor. If the processor tries to access data that is not in the cache, a cache miss occurs, and the data must be retrieved from a lower level of memory. Cache misses involve a performance penalty, which includes the clock cycle in which the miss occurs and the number of cycles spent recovering the requested data from memory. Accordingly, it may be desirable to provide a local addressable memory, e.g., an L1 SRAM, to store data and instructions in the processor core to improve access speed and reduce cache miss penalties.